As the demand increases for substrates or wafers to contain more and more devices, the number of interconnects in a substrate must increase. With complex integrated circuits, many oxide layers are deposited and more stacks are layered over the silicon base, forming interlevel stacks. Vias can be cut into these multilayered structures to permit interconnections between levels. These interlevel vias typically have a depth-to-width ratio greater than one and are termed high aspect ratio vias.
High aspect ratio features in vias or contacts permit a greater number of interlevel interconnects, but their depth makes it difficult to fill the via. For efficient interconnections between vias, the film deposited in the via must completely and uniformly coat both the bottom and sidewalls and must completely fill the via. Thus, the ability of a film to uniformly coat, form contact plugs and completely fill interlevel vias is important to the integrity and efficiency of the integrated circuit.
Typically, a metal layer of titanium (Ti) is first deposited into the via, followed by depositing a metal such as aluminum (Al) to fill the via. The Ti layer, ideally about 100 .ANG. but usually in the range of about 300 .ANG. to about 500 .ANG., serves as a wetting layer or seed layer for the subsequent Al or other metal deposition. The Ti layer also serves as a diffusion barrier to keep the metal in the metal oxide layer from diffusing into the silicon layer at the contact.
Al contact plugs require a barrier, usually titanium nitride (TiN) or titanium tungsten (TiW), and a wetting layer or seed layer of Ti. The TiN barrier is fortified by annealing, using either a furnace anneal or a reflow 20 module, to pack grain boundaries of the TiN to prevent electromigration. Al via plugs require only a seed or wetting layer such as Ti prior to a fill step.
The fill step can be by a "reflow", "two-step", "three-step", Forcefill, or chemical vapor deposition (CVD), for example a plasma enhanced chemical vapor deposition (PECVD), process. The fill steps occur at an elevated temperature (&gt;350.degree. C.) allowing TiAl.sub.3 to form in the reaction Ti+3Al.fwdarw.TiAl.sub.3.
While TiN can also act as a wetting layer, Ti is more desirable since TiN reacts with Al at higher temperatures. Additionally many subsequent anneals can form AIN, which is insulating. TiN is also thermodynamically unstable with respect to Al. However, Ti too has disadvantages as a wetting layer. A clean Ti surface, which is required for Al fill, reacts with Al when heated above 350.degree. C. and forms TiAl.sub.3. The change in volume from TiAl.sub.3 induces the problem of stress-related voiding. TiAl.sub.3 is also much more resistive than Al, resulting in a net increase in the line resistance.
A minimum amount of Ti is required to provide continuous sidewall and bottom coverage of high aspect ratio features. Especially with collimated sputtering technologies, this leads to surface or field thicknesses in excess of 500 .ANG.. A 500 .ANG. layer of Ti in the field reacts with approximately 1500 .ANG. of Al, which increases the line resistance. The contact resistance will also increase slightly by the conversion of Ti reacting with aluminum to form TiAl.sub.3 as previously described.
Thus a method to form a thin metal film in high aspect ratio features to produce an efficient substrate or wafer is desirable.